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3 3-3 features ? high speed parallel access to the serial st-bus ? parallel bus optimized for 68000 m p (mode 1) ? fast dual-port ram access (mode 2) access time: 120 nsec ? parallel bus controller (mode 3) - no external controller required ? flexible interrupt capabilities - two independent/programmable interrupt sources with auto-vectoring ? selectable 24 and 32 channel operation ? programmable loop-around modes ? low power cmos technology applications ? parallel control/data access to t1/cept digital trunk interfaces ? digital signal processor interface to st-bus ? computer to digital pabx link ? voice store and forward systems ? interprocessor communications description the st-bus parallel access circuit (stpa) provides a simple interface between mitels st-bus and parallel system environments. ordering information mt8920be 28 pin plastic dip mt8920bc 28 pin ceramic dip MT8920BP 28 pin plastic j-lead mt8920bs 28 pin soic -40 c to 85 c figure 1 - functional block diagram d7-d0 a4-a0 cs ds, oe r/ w, we dt a ck, b usy, dcs irq, 24/32 ia ck, ms1 a5, stch mms v ss v dd c4i f0i sto1 sti0 sto0 tx0 dual port ram 32 x 8 rx0 dual port ram 32 x 8 tx1 dual port ram 32 x 8 parallel- to-serial converter serial-to- parallel converter parallel- to-serial converter comp/ mux address generator parallel port interface interrupt registers control registers issue 6 june 1996 mt8920b st-bus parallel access circuit iso-cmos st-bus ? family
mt8920b cmos 3-4 figure 2 - pin connections pin description pin # name description ? 1 c4i 4.096 mhz clock. the st-bus timing clock used to establish bit cell boundaries for the serial bus. 2 f0i framing pulse. a low going pulse used to synchronize the stpa to the 2048 kbit/s st-bus stream. the ?rst falling edge of c4i subsequent to the falling edge of f0i identi?es the start of a frame. 3 ia ck interrupt acknowledge (mode 1). this active low input signals that the current bus cycle is an interrupt vector fetch cycle. upon receiving this acknowledgement, the stpa will output a user-programmed vector number on d 0 - d 7 indicating the source of the interrupt. ms1 mode select 1 (mode 2,3). this input is used to select the device operating modes. a low applied to this pin will select mode 3 while a high will select mode 2. (refer to table 1.) 4 sti0 st-bus input 0. this is the input for the 2048 kbit/s st-bus serial data stream. 5 cs chip select. this active low input is used to select the stpa for a parallel access . 6 ds data strobe (mode 1). this active low input indicates to the stpa that valid data is on the data bus during a write operation or that the stpa must output valid data on the data bus during a read operation. oe output enable (mode 2). this active low input enables the data bus driver outputs. oe output enable (mode 3). this active low output indicates that the selected device is to be read and that the data bus is available for data transfer. 7r/ w read/write (mode 1,2). this input de?nes the data bus transfer as a read (r/ w = 1) or a write (r/ w= 0) cycle. we write enable (mode 3). this active low output indicates the data on the data bus is to be written into the selected location of an external device. 8-12 a0-a4 address bus (mode 1,2). these inputs are used to select the internal registers and two-port memories of the stpa. a0-a4 address bus (mode 3). these address outputs are generated by the stpa and re?ect the position in internal ram where the information will be fetched from or stored in. addresses generated in this mode are used to access external devices for direct memory transfer. 28 pin j-lead 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 c4i f0i iack, ms1 sti0 cs ds, oe r/ w, we a0 a1 a2 a3 a4 a5, stch vss vdd mms dt a ck, b usy, dcs irq, 24/32 sto1 sto0 d7 d6 d5 d4 d3 d2 d1 d0 28 pin pdip/cerdip/soic 27 4 3 2 1 28 26 5 6 7 8 9 10 11 25 24 23 22 21 20 19 17 12 13 14 15 16 18 f0i ia ck, ms1 sti0 c4i vdd mms dt a ck, irq, 24/32 sto1 sto0 d7 d6 d5 d4 cs ds, oe r/ w, we a0 a1 a2 a3 a4 vss d0 d3 d2 d1 b usy, dcs a5, stch
cmos mt8920b 3-5 ? pin descriptions pertain to all modes unless otherwise stated. table 1. stpa modes of operation 13 a5 address bit a5 (mode 1). this input is used to extend the address range of the stpa. a5 selects internal registers when high and tx/rx rams when low. a5 address bit a5 (mode 2). this input is used to extend the address range of the stpa. a5 selects tx0/rx0 rams when low and tx1/rx0 rams when high. stch start of channel (mode 3). this signal is a low going pulse which indicates the start of an st-bus channel. the pulse is four bits wide and begins at the start of each valid channel. 14 v ss ground. 15-22 d0-d7 bidirectional data bus. this bus is used to transfer data to or from the stpa during a write or read operation. 23 sto0 st-bus output 0. this output supplies the output st-bus 2048 kbit/s serial data stream from tx0 two-port ram. 24 sto1 st-bus output 1. in modes 1 and 2 this output supplies the output st-bus 2048 kbit/s serial data stream from tx1 two-port ram. in mode 3, information arriving at sti0 is output here with one frame delay. 25 irq interrupt request (mode 1). this open drain output, when low, indicates when an interrupt condition has been raised within the stpa. 24/32 24 channel/32 channel select (mode 2,3). this input is used to select the channel con?guration in modes 2 and 3. a low applied to this pin will select a 24 (t1) channel mode while a high will select a 32 (cept) channel mode. 26 dt a ck data transfer acknowledge (mode 1). this open drain output is supplied by the stpa to acknowledge the completion of data transfers back to the m p. on a read of the stpa, dt a ck low indicates that the stpa has put valid data on the data bus. on a write, dt a ck low indicates that the stpa has completed latching the m ps data from the data bus. b usy busy (mode 2). this open drain output signals that the controller and the st-bus are accessing the same location in the dual-port rams. it is intended to delay the controller access until after the st-bus completes its access. dcs delayed chip select (mode 3). this low going pulse, which is four bit cells long, is active during the last half of a valid channel. this signal is used to daisy-chain together two stpas in mode 3 that are accessing devices on the same parallel data bus. 27 mms master mode select (reset). this schmitt trigger input selects between either mode 1 (mms = 1), or modes 2and 3 (mms = 0). if mms is pulsed low in mode 1 operation the control and interrupt registers will be reset. (refer to table 1.) during power-up, the time constant of the reset circuit (see fig. 8) must be a minimum of ?ve times the rise time of the power supply. 28 v dd power supply input. (+5v). mode mms ms1 mode of operation function 1 1 n/a m p peripheral mode the stpa provides parallel-to-serial and serial-to-parallel conversions through a 68000-type interface. two tx rams and one rx ram are available along with full interrupt capability. 32 channel or 24 channel support is available. control register 1, bit d 5 (ramcon) = 0 for 32 channel operation and d 5 (ramcon)= 1 for 24 channel operation. 2 0 1 fast ram mode the stpa provides a fast access interface to tx0, tx1 and rx0 rams. this mode is intended for full parallel support of 24 channel t1/esf trunks and 32 channel cept trunks. input 24/32 (pin 25) = 0 for 24 channel operation, input 24/32 (pin 25) = 1 for 32 channel operation. 300 bus controller mode the stpa will synchronously drive the parallel bus using the address generator and provide all data transfer signals. this mode is intended to support 24 or 32 channel devices in the absence of a parallel bus controller. input 24/32 (pin 25) = 0 for 24 channel operation, input 24/32 (pin 25) = 1 for 32 channel operation. pin description (continued) pin # name description ?
mt8920b cmos 3-6 functional description the stpa (st-bus parallel access) device provides a simple interface between mitels st-bus and parallel system environments. the st-bus is a synchronous, time division, multiplexed serial bussing scheme with data streams operating at 2048 kbit/s. the st-bus is the primary means of access for voice, data and control information to mitels family of digital telecommunications components, including north american and european digital trunk interfaces, isdn u and s digital line interfaces, ?lter codecs, rate adapters, etc. the stpa provides several modes of operation optimized according to the type of information being handled. for interfacing parallel data and control information to the st-bus, such as signalling and link control for digital trunks, the stpa provides a m p access mode (mode 1), and looks like a 68000 type peripheral. in this mode, the device provides powerful interrupt features, useful in monitoring digital trunk or line status (i.e., synchronization, alarms, etc.) or for setting up message communication links between microprocessors. to interface high speed data or multi-channel voice/ data to the st-bus for switching or transmission, the stpa has a high speed synchronous access mode (mode 2) and acts like a fast ram. for voice storage and forward, bulk data transfer, data buffering and other similar applications, the stpa has a controllerless mode (mode 3) in which it provides address and control signals to the parallel bus this is useful for performing direct transfers to the st-bus from external devices such as a ram buffer. the stpa is a two port device as shown in the functional block diagram in figure 1. the parallel port provides direct access to three dual port rams, two transmit and one receive. the address, data and control busses are used to communicate between the rams and a parallel environment. two parallel-to-serial converters, and one serial-to-parallel converter interface the dual port rams to the st-bus port of the stpa. this port consists of two serial output streams and one serial input stream operating at 2048 kbit/s. this con?guration of two outputs and one input was designed to allow a single stpa to form a complete control interface to mitels digital trunk interfaces (mt8976, mt8978 and mt8979) which have two serial input and one serial output control streams. st-bus clocking circuitry, address generator and various control and interrupt registers complete the stpas functionality. modes of operation the three basic modes of operation, m p peripheral mode (mode 1), fast ram mode (mode 2) and bus controller mode (mode 3) are selected using two external input pins. these inputs are mms and ms1 and are decoded as shown in table 1. whenever mms=1 the device resides in mode 1. in this mode, ms1 pin is unavailable and is used for a different function. when mms=0, modes 2 or 3 are selected as determined by input ms1. if ms1=1, mode 2 is selected and if ms1 =0, mode 3 is selected. each of the modes of the stpa provides a different pinout to ease interfacing requirements of different parallel environments. these are shown in figure 3 below. in m p peripheral mode the device uses interface signals consistent with a 68000-type m p bus. mode 2, fast ram mode, uses signals typical of standard ram type interfaces. mode 3 interface signals are very similiar to mode 2 signals except that the address and control signals are supplied as outputs by the stpa. figure 3 - modes 1, 2, 3 pin connections m p peripheral mode #1 fast ram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 c4i f0i iack sti0 cs ds r/ w a0 a1 a2 a3 a4 a5 vss vdd mms dt a ck irq sto1 sto0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 c4i f0i ms1 sti0 cs oe r/ w a0 a1 a2 a3 a4 a5 vss vdd mms b usy 24/32 sto1 sto0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 c4i f0i ms1 sti0 cs oe we a0 a1 a2 a3 a4 stch vss vdd mms dcs 24/32 sto1 sto0 d7 d6 d5 d4 d3 d2 d1 d0 mode #2 bus controller mode #3
cmos mt8920b 3-7 24/32 channel operation the stpa may be con?gured to operate as a 32 channel or 24 channel device. this feature, which is available in all three modes of operation, is particularly useful in applications involving data access to cept and t1 digital trunk interfaces. when used as a data interface to mitels cept digital trunks, the stpa maps the 32 consecutive bytes of each dual port memory directly to st-bus channels 0-31. this is performed by the address generator shown in the functional block diagram (see figure 1). figures 4 c & d show the relationship between relative dual port ram locations and corresponding st-bus channels, for both input and output serial streams, when the stpa is con?gured as a 32 channel device. when used as a data interface to mitels t1 trunk devices, however, only the ?rst 24 consecutive ram locations are mapped to 24 of the 32 st-bus channels. this mapping follows a speci?c pattern which corresponds with the data streams used by mitels t1 products. instead of a direct correlation (as in 32 channel operation), the 24 consecutive ram locations are mapped to the st-bus with every fourth channel, beginning at channel 0, set to ff 16 (ie. channel 0, 4, 8, 12, 16, 20, 24 and 28). figures 4 a & b show the relationship between ram locations and st-bus channel con?guration. this feature allows the stpa to be interfaced directly to mitels t1 trunk family. when the stpa is operated in mode 1, 24 and 32 channel con?gurations are selected using bit d 5 (ramcon) in control register 1. d 5 = 0 selects 32 channel operation and d 5 = 1 selects 24 channel operation. when the stpa is operated in modes 2 or 3, however, the channel con?guration is done using input 24/32 (pin 25). when 24/32 = 1 the device uses all 32 channels and when 24/32 = 0 it uses 24. dual port rams each of the three serial st-bus streams is interfaced to the parallel bus through a 32 byte dual port ram. this allows parallel bus accesses to be performed asynchronously while accesses at the st-bus port are synchronous with st-bus clock. as with any dual port ram interface between two asynchronous systems, the possibility of access contention exists. the stpa minimizes this occurrence by recognizing contention only when accesses are performed at the same time for the same 8-bit cell within the dual port rams. furthermore, the probability of contention is lessened since st-bus accesses require only the last half cycle of c4i of every channel. when contention does occur, priority is always given to the st-bus access. the stpa indicates this contention situation in a different manner for modes 1 and 2. in mode 1, the contention is masked by virtue of the "handshaking" method used to transfer data on this 68000-type interface. data strobe ( ds) and data transfer acknowledge ( dt a ck) control the exchange. if contention should occur the device will delay returning dt a ck and thus stretch the bus cycle until the m p access can be completed. in mode 2, if access is attempted during a "contention window" the stpa will supply the b usy signal to delay the start of the bus cycle. this contention window is de?ned as shown in figure 16. the window exists during the last cycle of c4i clock in each channel timeslot. although st-bus access is only required during the last half of this clock period, the contention window exists for the entire clock period since a parallel access occurring just prior to an st-bus access will not complete before the st-bus access begins. figure 16 further shows four possible situations that may occur when parallel accesses are attempted in and around the contention window. condition 1 indicates that an access occurring prior to the contention window but lasting into the ?rst half of it will complete normally with no contention arbitration. if the access should extend past the ?rst half of the contention window and into the st-bus access period, the b usy signal will be generated. conditions 3 and 4 show accesses occurring inside the contention window. these accesses will result in b usy becoming active immediately after the access is initiated and remaining active as shown in figure 16. access contention is non-existent in mode 3 since the parallel bus signals, driven by the stpa, are synchronized to the st-bus clocks. mode 1 - m p peripheral mode in mode 1, the stpa operates as an asynchronous 68000-type microprocessor peripheral. all three dual-port rams (tx0, tx1, rx0) are made available and may be con?gured as 32 or 24 byte rams. also available are the full complement of control and interrupt registers. the address map for mode 1 is shown in table 2. the stpa, in mode 1, uses signals cs, r/ w, ds (data strobe), dt a ck (data acknowledge) irq, and ia ck (interrupt acknowledge) at the parallel interface. the pinout of the device is shown in figure 3.
mt8920b cmos 3-8 figure 4 a) relative rx ram address vs. st-bus channel - 24 channel mode figure 4 b) relative tx ram address vs. st-bus channel - 24 channel mode figure 4 c) relative rx ram address vs. st-bus channel - 32 channel mode figure 4 d) relative tx ram address vs. st-bus channel - 32 channel mode x- unused channels marked x transmit ff 16 sti0 0 x 1234 x 5678 x 9 101112 x 13 14 15 16 x 17 18 19 20 x 21 22 23 24 x 25 26 27 28 x 29 30 31 relative ram location 0 1 2 3 4 5 6 7 8 9 1011 121314 151617 181920 212223 sto0 sto1 0 x 1234 x 5678 x 9 101112 x 13 14 15 16 x 17 18 19 20 x 21 22 23 24 x 25 26 27 28 x 29 30 31 relative ram location 0 1 2 3 4 5 6 7 8 9 1011 121314 151617 181920 212223 sti0 012345678910111213141516171819202122232425262728293031 relative ram location 012345678910111213141516171819202122232425262728293031 sto0 sto1 012345678910111213141516171819202122232425262728293031 relative ram location 012345678910111213141516171819202122232425262728293031
cmos mt8920b 3-9 table 2. mode 1 address map notes: x is dont care a 6 is bit d 4 of control register 1 table 3. control register 1 bit de?nitions address bits registers a 6 a 5 a 4 a 3 a 2 a 1 a 0 read write 0 ? ? ? 0 0 ? ? ? 0 0 ? ? ? 1 0 ? ? ? 1 0 ? ? ? 1 0 ? ? ? 1 0 ? ? ? 1 rx0 - channel 0 ? ? ? rx0 - channel 31 tx0 - channel 0 ? ? ? tx0 - channel 31 x100000 control register 1 control register 1 x100001 control register 2 control register 2 x100010 interrupt vector register interrupt vector register x100100 interrupt flag register 1 - x100101 interrupt flag register 2 - x100110 image register 1 - x100111 image register 2 - x101000 interrupt mask register 1 interrupt mask register 1 x101001 interrupt mask register 2 interrupt mask register 2 x101010 match byte register 1 match byte register 1 x101011 match byte register 2 match byte register 2 x101100 interrupt channel address 1 interrupt channel address 1 x101101 interrupt channel address 2 interrupt channel address 2 1 ? ? ? 1 0 ? ? ? 0 0 ? ? ? 1 0 ? ? ? 1 0 ? ? ? 1 0 ? ? ? 1 0 ? ? ? 1 rx0 - channel 0 ? ? ? rx0 - channel 31 tx1 - channel 0 ? ? ? tx1 - channel 31 bit name description 7 (unused) 6 irqrst interrupt reset. this bit, when set high, automatically clears the interrupt flag register and the interrupt image register without these registers being serviced. this bit automatically resets to zero after the register clear is completed. 5 ramcon ram con?guration. this bit con?gures tx0, tx1 and rx0 rams for 32 or 24 byte operation. d 5 = 0 for 32 channel; d 5 = 1 for 24 channel. 4a 6 address bit a6. this bit extends the addressing range for access to tx1 memory. 3 irq2mode interrupt source 2 mode select. this bit con?gures the source 2 interrupt generator. d 3 = 0 selects static interrupt mode; d 3 = 1 selects dynamic interrupt mode. 2 irq1mode interrupt source 1 mode select. this bit con?gures the source 1 interrupt generator. d 2 = 0 selects static interrupt mode; d 2 = 1 selects dynamic interrupt mode. 1 irq2en interrupt source 2 enable. irq2en = 1 enables interrupts to occur from source 2. 0 irq1en interrupt source 1 enable. irq1en = 1 enables interrupts to occur from source 1.
mt8920b cmos 3-10 timing information for data transfers on this interface is shown in figure 14. the mode 1 interface is designed to operate directly with a 68000-type asynchronous bus but can easily accommodate most other popular microprocessors as well. control registers two control registers allow control of mode 1 features. control register 1 provides bits to select the type of interrupt, to enable interrupts from two different and independent sources and to reset the interrupt registers. also contained in control register 1 are bits to con?gure the device for 24 or 32 channel operation and to expand the address range for convenient access to the second transmit ram tx1. a description of the bit functions in control register 1 is shown in table 3. mode 1 provides various loopback paths and output con?guration options which are controlled by bits in control register 2. bits d 0 , d 1 of control register 2 con?gure loopbacks using input and output streams sti0, sto0 as described in table 4. the input stream sti0 can be looped back to source the output stream sto0 as well as receive ram rx0. the transmit ram tx0 can be looped to source the receive ram rx0, as well as sto0 and, the transmit ram tx0 can be looped to the receive ram rx0 while sti0 sources sto0. the function of these loopback con?gurations is shown in figure 5. in a similar way, the output sto1 can be recon?gured for different functionality. bits d 2 and d 3 of control register 2 allow sto1 to be sourced, with a one frame delay via tx1 from receive stream sti0. sto1 can also output the result of a comparison of the contents of tx1 ram with input stream sti0. these output con?gurations of sto1 are shown in figure 6 a and b. figure 6 c shows the effect of combining these two features. interrupt registers interrupts can be generated in mode 1 only. two channels of the st-bus input stream, sti0, can be selected to provide an interrupt to the system. interrupts can be of two types: static or dynamic. static interrupts are caused when data within a selected channel matches a given pattern. dynamic interrupts occur when bits in a selected channel change state (1 to 0, 0 to 1 or toggle). interrupts are controlled through two identical paths (1 and 2) consisting of the following registers: interrupt channel address (1/2): the address (0-31) of the channel which will generate the interrupt is stored in this register. image register (1/2): the contents of the channel causing the interrupt is stored in this register. reading this register will clear its contents. match byte register (1/2): in static mode this register is used to store the byte which will be compared with the contents of the selected channel causing the interrupt. in dynamic mode, the bits in this register and the corresponding bit in the interrupt mask register de?ne the type of dynamic interrupt (i.e., 0 to 1, 1 to 0, toggle). (refer to table 5.) table 4. control register 2 bit de?nitions bit name description 7-4 (unused) 3-2 config sto1 output con?guration bits: d 3 d 2 = 00- normal operation. st-bus stream from tx1 is output on sto1 pin. 01- sti0 stream is output on sto1 pin delayed one frame (figure 6 a). 10- sti0 is compared through xor (exclusive or) with st-bus stream from tx1 and output at sto1 (figure 6 b). 11- sti0 stream, delayed one frame (via tx1), is compared (xor) with the next frame arriving at sti0 and the result output at sto1 (figure 6 c). 1-0 loopback internal loopback con?guration bits: d 1 d 0 = 00- normal operation. no internal loops. 01- loop sti0 to sto0 while still receiving sti0 in rx0 (figure 5 a). 10- loop tx0 output st-bus stream to rx0 input st-bus stream while outputting tx0 output to sto0. sti0 is not received (figure 5 b). 11- loop tx0 output st-bus stream to rx0 input st-bus stream. loop sti0 to sto0 (figure 5 c).
cmos mt8920b 3-11 figure 5 - loopback con?gurations interrupt mask register (1/2): in static mode the contents of this register masks bits in the match byte register that are dont care bits 1 - bit masked 0 - bit not masked in dynamic mode, each bit in this register and the corresponding bit in the match byte register de?ne what type of dynamic interrupt is selected. (refer to table 5.) interrupt flag register (1/2): in static mode the least signi?cant bit in this register is set to 1 to ?ag the corresponding path in which the interrupt occurs. in dynamic mode this register sets the bits which re?ect the position of the bits in the corresponding interrupt register which caused the interrupt. figure 6 - sto1 con?gurations interrupt vector register this register shown in figure 7 is common to both interrupt paths and stores an 8 bit vector number which will be output on the data bus when interrupt acknowledge ( ia ck) is asserted. bits labelled v 2 - v 7 are stored by the controlling m p. bits irq1 and irq2 are set by the stpa to indicate which path caused the interrupt. this creates unique vectors which are used by the m p to vector to interrupt service routines. this feature may be bypassed by simply not asserting ia ck during interrupt acknowledged. figure 7 - interrupt vector registers sto0 sti0 rx0 m p control register 2 bits d 1 = 0, d 0 = 1 a) sto0 sti0 tx0 rx0 m p control register 2 bits d 1 = 1, d 0 = 0 b) sto0 sti0 control register 2 bits d 1 = 1, d 0 = 1 m p tx0 rx0 c) d7 d6 d5 d4 d3 d2 d1 d0 v 7 v 6 v 5 v 4 v 3 v 2 irq2 irq1 sto0 sti0 sto1 sto0 sti0 sto1 sto0 sti0 sto1 m p m p m p tx0 rx0 tx1 1 frame delay tx0 rx0 tx1 tx0 rx0 tx1 1 frame delay control register 2 bits d 3 = 0, d 2 = 1 control register 2 bits d 3 = 1, d 2 = 0 control register 2 bits d 3 = 1, d 2 = 1 a) b) c)
mt8920b cmos 3-12 interrupt modes and servicing static interr upt mode a static interrupt is caused when an incoming byte matches a prede?ned byte. the incoming byte from a selected channel is stored in interrupt image register (1/2) where it is compared with the contents of the corresponding match byte register. the result of the comparison of individual bits is masked by the contents of the mask register (1/2) before it is used to generate an irq. after a static interrupt occurs, information in the interrupt image register is frozen until the m p performs a read operation on this register. when servicing static interrupts assertion of ia ck will cause the contents of the vector register, with the irq1 or irq2 bit set, to be output on the data bus. the service routine can subsequently clear irq by reading the interrupt image register. alternatively, the irqrst bit in control register 1 can be set to clear the associated interrupt registers. static interrupts are selected using irq1mode and irq2mode bits in control register 1. interrupts are then enabled to the irq pin with irq1en and irq2en bits of the same register. dynamic interr upt mode a dynamic interrupt is generated by a change of state of bits in a selected channel. a 0 to 1 transition or a 1 to 0 transition or a simple change of state from the previous state (toggle) can be detected. the type of transition to be detected is selected using two bits, one from the match byte register (1/2) and one from the interrupt mask register (1/2), in the corresponding bit positions. table 5 shows how the two registers are programmed. table 5 - dynamic interrupt types for example, the following steps are required to generate an interrupt when bit d 3 of channel 4 changes state from 0 to 1 (all other bits are masked): (channel 4 of sti0 selected) (when bit d 3 toggles 0 to 1) dynamic interrupts from interrupt path 1 would then be enabled using the control register 1. this would cause interrupt 1 path to be enabled while interrupt 2 path is disabled. as with static interrupts, upon serving a dynamic interrupt, assertion of ia ck will cause the contents of the vector register, with the appropriate path bit set, to be output on the data bus. the information contained in the channel is frozen in the interrupt image register. to clear a dynamic interrupt, however, the m p must read the interrupt flag register of the path responsible for the interrupt to determine which bit caused the interrupt. the bit in the corresponding position will be set to 1 and reading this register will clear its contents. alternatively, as with static interrupts, the irqrst bit in control register 1 can be set to clear the image interrupt register, flag register and path bits in the vector register. dynamic interrupts are selected using irq1mode and irq2mode bits in control register 1 and are enabled using irq1en and irq2en in the same register. mms pin reset the stpa can be reset in mode 1 using the mms pin (27). applying a low pulse (0v) to mms after power is applied to the device will reset all control and interrupt registers to 00 16 . this can be accomplished on power up with a simple r-c circuit as shown in figure 8. figure 8 - mms reset function match byte register bit d x mask byte register bit d x transition type detected on incoming bit d x (x = 0 ....7) 0 0 1 1 0 1 0 1 mask bit d x 0 to 1 transition 1 to 0 transition toggle d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 channel address register 1 = 00000100 match byte register 1 = 00000000 interrupt mask register 1 = 00001000 control register 1 = 00000101 v dd r mms stpa 27 c
cmos mt8920b 3-13 mode 2 - fast ram mode mode 2 operates as a high speed dual port ram interface to the st-bus. only the two transmit rams, tx0 and tx1, and the receive ram, rx0 are active in this mode (i.e., control registers and interrupt registers are inactive). the main feature of this mode is fast access to the dual-port rams. fast access allows high-speed controllers to use this device as a data interface to t1 and cept digital links. timing information is shown in figure 15. mode 2 can also support 24 channel and 32 channel operation. the channel con?guration is selected using 24/32 pin. when 24/32=0 the device operates in 24 channel mode and when 24/32=1, it operates in 32 channel mode. the physical interface in this mode resembles that of a simple ram device. the signals used to read and write the device are cs, oe, r/ w. the pinout of the stpa in this mode is shown in figure 3. address decoding for tx0, tx1, rx0 is shown in table 6. contention can arise for access to the dual port rams. the occurrence of this is minimized since the st-bus serial-to-parallel and parallel-to-serial converters require ram access for only 1/32 of a channel time (i.e., last half cycle of c4i for each channel). for contention to occur the high speed controller must access the same ram location as that of the st-bus. for a parallel read operation this corresponds to the current st-bus channel and for a write operation, the next st-bus channel. access contention in mode 2 is arbitrated with the b usy signal. b usy is intended to hold off any parallel access cycle until it again goes inactive. figure 16 shows how the access is arbitrated for accesses near the contention window. applications using high speed access can easily avoid generating b usy by co-ordinating channel reads and writes with framing and channel boundary information. mode 3 - parallel bus controller in this mode the stpa outputs all necessary signals required to drive devices attached to the parallel port. the stpa can be used to drive devices such as rams, fifos, latches, a/d and d/a converters, and codecs, directly from the st-bus without an intervening m p. as with the other modes, mode 3 can operate from 32 channels or 24 channels by connecting 24/32 high or low, respectively. this allows devices to be driven remotely via a t1 or cept digital trunk link when used with mitels trunk products. referring to figure 1, the address generator block generates and drives the external address lines a4-a0. the stpa also generates oe (output enable) and we (write enable) to facilitate data transfers from rx0 ram and to tx0 ram. tx1 ram is unavailable in this mode. the stpa, in mode 3, generates external addresses in a particular sequence that minimizes throughput delay through the device. when channel n is present on the st-bus, the stpa generates address n+1 on the address bus and asserts oe to output data from an external device and latch it into the stpa. during the same channel n, the stpa will generate address n-1 with we asserted to write from the stpa to an external device. timing for mode 3 transfers is shown in figure 17. all parallel bus signals are synchronized to the st- bus clock. the device must be selected using cs in order for the parallel bus drivers to be enabled. cs should remain active for four st-bus bit periods (8 x c4i cycles) since a read and a write operation require 2 bit periods each. the stpa generates a signal stch (start of channel) which becomes active at the start of each channel and remains active for 1/2 of the channel time (figure 18). this signal may be table 6. mode 2 address map address bits registers a 5 a 4 a 3 a 2 a 1 a 0 read write 0 ? ? ? 0 0 ? ? ? 1 0 ? ? ? 1 0 ? ? ? 1 0 ? ? ? 1 0 ? ? ? 1 rx0 - channel 0 ? ? ? rx0 - channel 31 tx0 - channel 0 ? ? ? tx0 - channel 31 1 ? ? ? 1 0 ? ? ? 1 0 ? ? ? 1 0 ? ? ? 1 0 ? ? ? 1 0 ? ? ? 1 rx0 - channel 0 ? ? ? rx0 - channel 31 tx1 - channel 0 ? ? ? tx1 - channel 31
mt8920b cmos 3-14 connected directly to cs to enable the device appropriately. figure 9 - "daisy-chained" stpas in 32 channel parallel bus controller mode (mode 3) in order to facilitate ef?cient use of the parallel bus another signal, similar to stch, is supplied by the stpa. delayed chip select ( dcs) becomes active for the last half of each channel (figure 19). this may be connected to a second stpa, residing on the same physical parallel bus, enabling it to perform its read/write operations in the second half of each channel. this allows a large number of devices, connected on a common bus, to be driven by two st-bus streams. figure 9 shows how this "daisy chaining" of stpas is implemented while figure 10 illustrates the timing on the shared parallel bus. applications parallel pbx to digital trunk interface the stpa is an ideal component for interfacing parallel pbx environments to mitels family of digital trunk devices. figure 11 shows a typical interface for both t1/esf and crc-4 cept digital trunks to a system utilizing a parallel bus architecture. both the mh89760b t1/esf and the mh89790b crc-4 cept trunk modules are shown interfaced to a parallel bus structure using two stpas operating in modes 1 and 2. the ?rst stpa operating in mode 2 (mms=0, ms1=1, 24/32=0), routes data and/or voice information between the parallel telecom bus and the t1 or cept link via dsti and dsto. the second stpa, operating in mode 1 (mms=1) provides access from the signalling and link control bus to the mh89760b or mh89790b status and control channels. all signalling and link functions may be controlled easily through the stpa transmit rams tx0, tx1, while status information is read at receive ram rx0. in addition, interrupts can be set up to notify the system in case of slips, loss of sync, alarms, violations, etc. common bus 00 1 oe we a0 a1 a2 a3 a4 cs dcs 00 1 oe we a0 a1 a2 a3 a4 cs stch sti0 sto0 sti0 sto0 mms ms1 24/32 mms ms1 24/32 figure 10 - timing relationship for mode 3 daisy chaining bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n + 1 n - 1 n + 1 n - 1 in out in out st-bus c4i address oe we data bus stch dcs channel n
cmos mt8920b 3-15 figure 11 - typical t1-esf / crc-4 cept digital trunk con?guration high speed bus telecom parallel signalling and link bus control mt8920b (mode 2) d 0 -d 7 a 0 -a 5 cs r/ w oe sto0 sti0 sto1 c4i f0i mms ms1 24/32 mt8920b (mode 1) d 0 -d 7 a 0 -a 5 cs r/ w dt a ck sto0 sti0 sto1 c4i f0i mms ds irq ia ck +5v +5v ?? +5v ? mt8977/79 dsti dsto csti0 csto csti1 f0i c2i c1.5i ? txa txb rxa rxb rxd e1.5i ? (e2i ?? ) e8ko clock extractor tx line driver rx line receiver dip switch equ mh89761* mt8940 ? c1.5o ? f0i ? c2o f0b c4b c8kb 12.355 ? mhz osc. 16.388 mhz osc. mh89760b/790b notes: ? signals applicable to t1-esf applications using mt8977 and mh89760b ?? signals applicable to crc-4 cept applications using mt8979 and mh89790b * equalizer mh89761 available for t1/esf applications
mt8920b cmos 3-16 digital signal processor to st-bus interface mode 2 allows many high speed devices to be easily connected to the st-bus. figure 12 shows a tms32020 digital signal processor interfaced to the st-bus through the stpa. this simple interface allows complex functions to be implemented in such systems as pbxs and computer systems. some of the possible functions include: - digital filtering - voice conferencing - speech/data compression - encryption - tone detection and generation - frequency spectrum analysis - image processing - m -law to a-law conversion - echo cancellation - modulation - speech synthesis and recognition figure 12 - st-bus to dsp interface tms32020 mt8920b 74hct 138 ds a8-a0 d7-d0 strb r w msc ready a9 a8 a7 a6 e2 e1 a b c cs a5-a0 d7-d0 oe we sto0 sti0 sto1 mms ms1 24/32 +5v +5v
cmos mt8920b 3-17 connecting the stpa to a shared st-bus line the stpas sto0 and sto1 outputs cannot be directly forced into a high impedance state. however, with some external logic, the sto0 output can be buffered by a three-state device, controlled by the sto1 output. this application is only possible if the tx1 ram and associated sto1 output are not required for some other purpose. figure 13 shows an external buffer u1 controlled by the sto1 output and an external output data enable (ode) signal. when ff (hex) is written to the tx1 ram, the corresponding sto1 output channel goes to logic high. this signal, and-ed together with a logic high at ode, enables u1, resulting in the sto0 signal transparently passed to the output of u1. when 00 (hex) is written to the tx1 ram, the sto1 output goes logic low. this disables u1, resulting in a high impedance state at the output of u1, corresponding to the selected channel. this method of three-state buffering permits output control on a per-channel or per-bit basis. the ode input is used to enable the st-bus outputs after all st-bus devices are properly con?gured by software. this eliminates the possibility of contention on the st-bus lines during the power-up state. figure 13 - connecting stpa to a common st-bus line parallel port ode parallel port sto0 sto1 mt8920b mt8980 sti0 sti1 sti7 sto7 sto1 sto0 ode 74hc125 74hc00 u1 st-bus u2
mt8920b cmos 3-18 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. ? typical ?gures are at 25 c and are for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings* - voltages are with respect to ground (v ss ) unless otherwise stated. parameter symbol min max units 1 supply voltage v dd -0.3 7.0 v 2 voltage on any i/o pin -0.3 v dd + 0.3 v 3 current on any i/o pin i i/o 25 ma 4 storage temperature t st -55 125 c 5 package power dissipation cerdip plastic p d p d 1000 600 mw mw recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 supply voltage v dd 4.75 5.0 5.25 v 2 input high voltage v ih 2.4 v dd v for 400mv noise margin 3 input low voltage v il 0 0.4 v for 400mv noise margin 4 operating temperature t a -40 25 85 c 5 operating clock frequency f ck 4.096 mhz dc electrical characteristics - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym min typ ? max units test conditions 1 supply current static dynamic i ccs i ccd 10 510 m a ma outputs unloaded @f ck = 4.096 mhz 2 input high voltage v ih 2.0 v 3 input low voltage v il 0.8 v 4 input leakage current i z 10 m av dd =5.25v, v in =v ss to v dd 5 input capacitance c in 10 pf 6 schmitt trigger input high (mms) v t+ 3.8 3.0 v 7 schmitt trigger input low (mms) v t- 2.0 1.0 v 8 schmitt trigger hysteresis (mms) v h 0.8 1.0 v 9 output high current (except irq ) i oh 10 15 ma v oh = 2.4v, v dd = 4.75v 10 output low current (except irq) i ol 510 mav ol = 0.4v, v dd = 4.75v 11 irq, dt a ck, b usy sink current i ol 10 15 ma v ol = 0.4v, v dd = 4.75v 12 tristate leakage a 4 -a 0 , oe, we (mode 3) i oz 1 10 m av dd = 5.25v v out = v ss to v dd 13 open drain off-state current irq, dt a ck, b usy i off 1 20 m av dd = 5.25v v out = v dd 14 output capacitance c o 15 pf
cmos mt8920b 3-19 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c, v dd =5v, t clk =244 ns, t ch =t cl =122 ns and are for design aid only: not guaranteed and not subject to production testing. ??the cycle is initiated by the falling edge of cs or ds, whichever occurs last. timing is relative to the last falling edge which initiates the cycle. (1) t cwm is equal to t ch or t cl whichever is smaller (some st-bus compatible transceivers may generate c4 clock having t chmin =70ns or t clmin =70ns. (2) worst case access when memory contention occurs. figure 14 - mode 1 parallel bus timing ? during interrupt acknowledge cycle ia ck replaces cs. r/ w must remain high. ac electrical characteristics ? - mode 1 parallel bus timing (see fig. 14) (v cc =5.0v 5%,t a =-40 to 85 c) characteristics sym min typ ? max units test conditions 1 address to ds ( cs) low ?? t ards 0ns 2r/ w to ds ( cs) low ?? t rwds 20 ns 3 ds ( cs) low to dt a ck low ?? t rds 1,2 t cwm t clk 2*t clk ns load c 4 valid data to dt a ck low (read) t rd t cwm -30 ns load a, c l =130pf, r l =740 w 5 ds high to dt a ck high t dar 65 ns load c, c l =50pf 6 ds high to data high imped.(read) t dhz 045ns load a, c l =130pf, r l =740 w 7 ds high to cs high t csh 0ns 8 data hold time (write) t dht 0ns 9 input data valid after ds t dst t cwm -30 ns 10 address hold time ?? t adht 50 ns a0 - a5 cs ( ia ck ? ) r/ w ds dt a ck d0 - d7 d0 - d7 t adht t ards t rwds t rds t rd t dst t dht data in data out t dhz t dar t csh
mt8920b cmos 3-20 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c, v dd =5v, t clk =244 ns, t ch =t cl =122 ns and are for design aid only: not guaranteed and not subject to production testing. figure 15 - mode 2 timing diagram (no contention) ac electrical characteristics ? - mode 2 parallel bus timing - (see figures 15 and 16) (v cc =5.0v 5%,t a =-40 to 85 c) characteristics sym min typ ? max units test conditions 1 oe low to valid data t evd 60 ns load a, c l =130pf, r l =740 w 2 address access time t aa 120 ns load a, c l =130pf, r l = 740 w 3 cs low to valid data t csd 60 ns load a, c l =130pf, r l =740 w 4 output disable t ohz 50 ns load a, c l =130pf, r l =740 w 5 address setup time t asf 20 ns 6 data setup time t dst 30 ns 7 data hold time t dht 5ns 8 address hold time t ah 50 ns 9 write pulse width t wp 50 ns 10 oe, r/ w high to c4i high t ec4h -10 ns 11 oe, r/ w low to c4i low t ec4l 10 ns 12 c4i high to busy low t c4bl 50 ns load c 13 c4i low to busy high t c4bh 50 ns load c 14 oe, r/ w high to busy low t ebl 40 ns load c t ah t asf t wp t ohz t dst t dht t evd t csd t aa data in data out a0 - a5 cs oe r/ w d0 - d7
cmos mt8920b 3-21 figure 16 - mode 2 access contention resolution channel n - bit 0 c4i a0 - a5 cs condition 1: oe, r/ w b usy condition 2: oe, r/ w b usy condition 3: oe, r/ w b usy condition 4: oe, r/ w b usy channel (n + 1) - bit 7 st-bus access contention window read address n or write address (n + 1) (n matches incoming st-bus channel) access begins before contention window and finishes before st-bus access - no contention. access begins before contention window and continues into st-bus access. access begins within contention window but before st-bus access. access begins during st-bus access t ec4h t ec4l t c4bl t c4bh t ec4l t ebl t c4bh t ebl t c4bh
mt8920b cmos 3-22 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c, v dd =5v,t clk =244ns, t ch =t cl =122ns and are for design aid only: not guaranteed and not subject to production testing. figure 17 - mode 3 timing diagram ac electrical characteristics ? - mode 3 timing (see fig.17, 18 and 19) ((v cc =5.0v 5%,ta=-40 to 85 c) characteristics sym min typ ? max units test conditions 1 cs to oe, we, address enabled t zr 50 ns load a, c l = 130pf, r l = 740 w 2 c4i low to address change t acs 110 ns load a, c l = 130pf, r l = 740 w 3 cs to oe, we, address disabled t rz 50 ns load a, c l = 130pf, r l = 740 w 4 c4i low to output enable low t oed 75 ns load a, c l = 130pf, r l = 740 w 5 c4i low to output enable high t oeh 75 ns load a, c l = 130pf, r l = 740 w 6 oe, we, pulse width t enpw 2*t clk ns load a, c l = 130pf, r l = 740 w 7 c4i low to write enable low t wed 75 ns load a, c l = 130pf, r l = 740 w 8 c4i low to write enable high t weh 75 ns load a, c l = 130pf, r l = 740 w 9 read data valid from oe t rst (2*t clk ) -60 ns 10 read data hold time t rht 0ns 11 write data setup time t wst 70 100 ns load a, c l = 130pf, r l = 740 w 12 write data hold time t wht 70 100 ns load a, c l = 130pf, r l = 740 w 13 c4i transition to stch, dcs trans. t stc 120 ns load a, c l = 70pf, r l = 1.22k w 14 stch pulse width t scpw 1830 ns load a, c l = 70pf, r l = 1.22k w 15 dcs pulse width t cspw 1830 ns load a, c l = 70pf, r l = 1.22k w channel n bit 7 (bit 3) bit 6 (bit 2) bit 5 (bit 1) bit 4 (bit 0) c4i a4 - a0 oe we d7 - d0 cs n + 1 n - 1 data in data out t acs t oed t oeh t enpw t wed t weh t enpw t wht t wst t rht t rst t zr t rz
cmos mt8920b 3-23 figure 18 - mode 3 stch timing diagram figure 19 - mode 3 dcs timing diagram channel n-1 channel n bit 0 bit 7 bit 6 bit 5 bit 4 c4i stch t stc t stc t scpw channel n channel bit 4 bit 3 bit 2 bit 1 bit 0 c4i stch dcs t stc t stc t cspw n+1
mt8920b cmos 3-24 ? timing is over recommended temperature & power supply voltages. ? typical ?gures are at 25 c, v dd =5v and are for design aid only: not guaranteed and not subject to production testing. figure 20 - st-bus timing diagram ac electrical characteristics ? - st-bus timing (see figure 20) (v cc = 5.0v 5%, t a = -40 to 85 c) characteristics sym min typ ? max units test conditions 1 clock c4i period t clk 244 ns 2 clock c4i period high t ch 70 122 ns 3 clock c4i period low t cl 70 122 ns 4 c4i rise time t r 20 ns 5 c4i fall time t f 12 ns 6 frame pulse setup time t fps 20 ns 7 frame pulse hold time t fph 20 ns 8 sto0/1 delay from c4i t sod 100 ns load b 9 sti0 setup time t sts 20 ns 10 sti0 hold time t sth 35 ns bit cell c4i f0i sto0 sto1 sti0 t cl t clk t ch t r t f t fps t fph t sod t sts t sth
cmos mt8920b 3-25 figure 21 - format of 2048 kbit/s st-bus streams figure 22 - waveform test point reference figure 23 - test load circuits channel 31 channel 0 channel 30 channel 31 channel 0 (8/2.048) m s bit d 7 on data bus bit d 0 on data bus bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 125 m s inputs 2.0 v 0.8 v outputs 2.0 v 0.8 v c l 6.0k r l v dd in4148 load a c l =150pf v dd 500 w c l =130pf load b load c
mt8920b cmos 3-26 notes:

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